The present invention relates to a method of designing a semiconductor integrated circuit device. More particularly, it relates to an approach to improving the efficiency of the overall design process, while reducing power consumption.
In the design of a semiconductor integrated circuit device, high-level synthesis has been performed conventionally by the process of gradually specifying, in a programming language, the individual components of the semiconductor integrated circuit device and the functions thereof in accordance with the specifications, behavior, RT, and the like of the semiconductor integrated circuit. After the high-level synthesis, logic synthesis is performed in accordance with design data described in an HDL to generate a logic circuit (net list) and then placement and routing is performed. At this stage, the specific circuit components and wires are becoming apparent so that an optimization process utilizing the estimation of power consumption, a processing speed, and the like effected by simulation is performed.
For example, the optimization process is performed in consideration of a tradeoff between the operating speed of a circuit and a chip area.
However, with the advent of a large-scale semiconductor integrated circuit device such as a system LSI in recent years, the degree of optimization after logic synthesis varies depending on the degree of properness with which the design has been performed in high-level synthesis preceding the logic synthesis. This is because, since block partitioning and the like have been performed almost definitely prior to the logic synthesis, the flexibility with which a change is permitted in the subsequent optimization process is low.
In the conventional design of a semiconductor integrated circuit device, however, whether or not high-level synthesis is proper depends on the skillfulness of the designer and means for optimization in the high-level synthesis remains undeveloped. This presents a serious obstacle to implementing more efficient design after logic synthesis.
It is therefore an object of the present invention to improve the efficiency of the overall design process by providing means for optimizing high-level synthesis and implement the design of a semiconductor integrated circuit device which is particularly low in power consumption. A method of designing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) inputting an application program including a behavioral description for designing the semiconductor integrated circuit device, partitioning, on a function-by-function basis, the application program including the behavioral description into blocks in which HW resources are to be placed, and generating an HW resource connection graph representing respective positions of the HW resources in each of the blocks and wires connecting the individual blocks; (b) inputting at least data on respective sizes of the HW resources from an HW library, provisionally placing the HW resources which are the HW resource connection graph, and outputting provisional placement data; (c) calculating, as weights of signal lines between blocks, ratios of a parameter between the individual wires connecting the blocks which affects at least either one of power consumption and each wire delay; (d) judging whether or not each of the weights of signal lines between blocks is equal to or less than a threshold value; and (e) outputting, when each of the weights of signal lines between blocks becomes equal to or less than the threshold value, an RTL logic circuit described in an HDL, the generation of the blocks in the step (a) and the steps (b) to (d) being repeatedly performed till each of the weights of signal lines between blocks is judged equal to or less than the threshold value in the step (d).
In accordance with the method, it becomes possible to perform effective block partitioning which allows optimization of a parameter affecting power consumption and delay to be judged quantitatively instead of block partitioning based on a description in an application program or on the experience of the designer. This allows placement and routing and the like to be performed by placing blocks resulting from rather proper partitioning on the low level design and thereby improves the efficiency of the overall design.
In the method of designing a semiconductor integrated circuit device, the step (a) includes the sub-steps of: (a1) partitioning the description in the application program into blocks representing tasks and generating a first data flow chart showing data flows between the individual tasks; (a2) simulating the application program; (a3) calculating, as first weight of signal lines between blocks, ratios between transition frequencies in the respective wires between blocks obtained in the sub-step (a2); (a4) judging whether or not each of the initial weights of signal lines between blocks is equal to or less than an initial threshold value; (a5) generating, when the initial weight of signal lines between blocks becomes equal to or less than the initial threshold value, a second data flow chart to allow the HW resources stored in the HW library to be placed in each of the blocks in the first data flow chart; and (a6) determining an execution timing for each of the blocks in the second data flow chart and placing the HW resources to generate the HW resource connection graph, block repartitioning in the sub-step (a1) and the sub-steps (a2) to (a4) being repeated till the initial weight of signal lines between block becomes equal to or less than the initial threshold value. As a consequence, block partitioning using characteristics inherent to the application is roughly optimized first and then fine block repartitioning using the provisional placement data is performed. This improves the efficiency of block partitioning performed in two stages.
In the method of designing a semiconductor integrated circuit device, the step (a) includes the sub-steps of: (a1) partitioning the description in the application program into modules each composed of a plurality of operational functions and generating a first data flow chart showing data flows between the individual modules; (a2) simulating the application program; (a3) calculating, as first weights of signal lines between modules, ratios of a parameter between respective wires connecting the modules obtained in the sub-step (a2) which affects at least either one of power consumption and each wire delay; (a4) grouping the plurality of modules into the plurality of blocks each composed of the plurality of modules; (a5) generating a second data flow chart which allows the HW resources stored in the HW library to be placed in each of the modules in the first data flow chart; and (a6) determining an execution timing for each of the modules in the second data flow chart and allocating the HW resources to generate the HW resource connection graph and the step (c) includes calculating second weights of signal lines between modules from the provisional placement data and the first weights of signal lines between modules and designating, as the weights of signal lines between blocks, the respective second weights of signal lines between modules of the wires connecting the blocks. As a consequence, modules as small circuit units composing the blocks are generated first and then the plurality of generated modules are combined to generate the blocks. This reduces constraints placed on block generation and module generation and allows optimum generation of the modules and blocks in accordance with the first CDFG.
In the method of designing a semiconductor integrated circuit device, the step (a) includes the sub-steps of: (a1) analyzing the description in the application program to generate a first data flow chart showing data flows between operational functions each implementing a behavior to allow the HW resources stored in the HW library to be placed; (a2) generating, from the plurality of operational functions, modules each composed of the plurality of operational functions and generating, from the first data flow chart, a second data flow chart showing data flows between the individual modules; (a3) simulating the application program; (a4) calculating, as first weights of signal lines between modules, ratios of a parameter between respective wires connecting the modules which affects at least either one of power consumption and each wire delay; (a5) grouping the plurality of modules into the plurality of blocks composed of the plurality of modules; and (a6) determining an execution timing for each of the modules in the second data flow chart and allocating the HW resources to generate the HW resource connection graph and the step (c) includes calculating second weights of signal lines between modules from the provisional data and the first weights of signal lines between modules and designating, as the weights of signal lines between blocks, the respective second weights of signal lines between modules of the wires connecting the blocks.
As a consequence, so-called transformation is performed prior to module generation. This adds optimization by the transformation to module generation.
In the method of designing a semiconductor integrated circuit device, the step (a) includes the sub-steps of: (a1) analyzing the behavioral description in the application program to generate a first data flow chart showing data flows between operational functions to allow the HW resources stored in the HW library to be placed; (a2) determining an execution timing for each of the operational functions in the first data flow chart and allocating the HW resources to generate the HW resource connection graph; (a3) generating, from the plurality of operational functions, modules each composed of the plurality of operational functions; (a4) simulating the application program; (a5) calculating, as first weights of signal lines between modules, ratios of a parameter between respective wires connecting the modules obtained in the sub-step (a3) which affects at least either one of power consumption and each wire delay; and (a6) grouping the plurality of modules into the plurality of blocks each composed of the plurality of modules and the step (c) includes calculating second weights of signal lines between modules from the provisional placement data and the first weights of signal lines between modules and designating, as the weights of signal lines between blocks, the second weights of signal lines between blocks. As a consequence, module generation and block generation are performed by using data obtained from so-called transformation and binding. This adds optimization by the transformation and binding to module generation.
The method of designing a semiconductor integrated circuit device further comprises, after the step (e), the steps of: (f) performing logic synthesis using design data described in the HDL to represent data on the blocks and a wiring structure between the blocks in a net list; and (g) performing placement and routing using the net list and outputting layout data, wherein the placement and routing is performed in the step (g) by using, as position determining data, the provisional placement data obtained in the step (b) and data on the blocks obtained in the step (c). This allows prompt placement and routing to be performed by placing blocks resulting from partitioning in high-level synthesis.
The method of designing a semiconductor integrated circuit device further comprises, after the step (e), the steps of: (f) performing logic synthesis using design data described in the HDL to represent data on the modules and a wiring structure between the modules in a net list; and (g) performing placement and routing using the net list and outputting layout data, wherein placement and routing is performed in the step (g) by using the provisional placement data obtained in the step (b) and data on the blocks obtained in the step (c) and after the step (e) and before the step (f), RTL simulation is performed and data resulting from the RTL simulation is feedbacked to the step (c). This allows more proper block partitioning to be performed based on data using the HDL data.
The method of designing a semiconductor integrated circuit device further comprises, after the step (e), the steps of: (f) performing logic synthesis using design data described in the HDL to represent data on the modules and a wiring structure between the modules in a net list; and (g) performing placement and routing using the net list and outputting layout data, wherein placement and routing is performed in the step (g) by using the provisional placement data obtained in the step (b) and data on the blocks obtained in the step (c) and after the step (f) and before the step (g), provisional wiring using the net list and simulation with provisional wiring load using a result of the provisional wiring are performed and data obtained as a result of the simulation with provisional wiring load is feedbacked to the step (c). This allows more proper block partitioning to be performed based on the provisional wire load.
The method of designing a semiconductor integrated circuit device further comprises, after the step (e), the steps of: (f) performing logic synthesis using design data described in the HDL to represent data on the modules and a wiring structure between the modules in a net list; and (g) performing placement and routing using the net list and outputting layout data, wherein placement and routing is performed in the step (g) by using the provisional placement data obtained in the step (b) and data on the blocks obtained in the step (c) and after the step (g), simulation with actual wire load using the layout data is performed and data obtained as a result of the simulation with actual wire load is feedbacked to the step (c). This allows more proper block partitioning to be performed based on the actual wire load.
More preferably, any two or more of the data obtained as a result of the RTL simulation, the data obtained as a result of the simulation with provisional wiring load, and the data obtained as a result of the actual wire load are feedbacked.
In the step (c), respective contribution rates of lengths of the wires between blocks are designated as the weights of signal lines between blocks. This allows block partitioning to be performed in consideration of delay.
In the step (c), respective contribution rates of capacitances of the wires between blocks are designated as the weights signal lines between blocks.
In the step (c), respective contribution rates of transition frequencies of the wires between blocks are designated as the weights of signal lines between blocks. This also allows block partitioning to be performed in consideration of a reduction in power consumption.
In the step (c), respective contribution rates of lengths and transition frequencies of the wires between blocks are more preferably designated as the weights of signal lines between blocks.
By feedbacking the data obtained as a result of the RTL simulation, the data obtained as a result of the simulation with provisional wiring load, the data obtained as a result of the actual wire load, or the like to the sub-step (a1) in the step (a), block partitioning can be performed after performing optimum transformation by using the result of simulation on the low level design.
By feedbacking the data obtained as a result of the RTL simulation, the data obtained as a result of the simulation with provisional wiring load, the data obtained as a result of the actual wire load, or the like to the sub-step (a2) in the step (a), block partitioning can be performed after performing optimum allocation and binding by using the result of simulation on the low level design.